The purpose of the front-end electronics coordination activity is to define and specify a common architecture of the front-end electronics implementation in the different sub-detectors of LHCb such that they can work together as a homogenous system. The implementation of the front-end electronics of each sub-detector must conform to the defined architecture in such a way that the behavior of each front-end system can be predicted from the general architecture definition. To improve the predictability of the whole system it is strongly promoted to use common solutions ( modules, interfaces, front-end chips, etc ) thereby also minimizing the required resources and manpower needed during the development and debugging phase.
A predictable behavior of the total front-end electronics system is of special importance in the LHCb experiment because of the high bunch crossing rate (40 MHz) and the relatively high level 0 trigger rates ( ~1Mhz). All front-ends must be perfectly synchronized to the beam crossing to insure correct capture of the detector signals. The arrival of the L0 trigger accept must be in perfect synchronization with the bunch crossing clock to insure the extraction of correct event data from the level 0 pipeline. Caused by the relative high level 0 trigger accept rate, event data from the Level 0 pipeline must be temporarily stored in a derandomizer buffer before being transferred to the L1 buffer. The size of this derandomizer buffer and the speed of which data can be transferred to the L1 buffer is a major bottleneck in the LHCb front-end which has a significant impact on the physics performance of the experiment. The L0 trigger accept rate must be limited centrally based on an emulation of the L0 derandomizer buffers. For a such a scheme to work reliable for a large system with more than 1 million channels, it is required that the L0 pipeline and the L0 derandomizer works in perfect synchronization across the whole experiment. Alternatively one would have to reduce the L0 trigger rate significantly to insure that no buffers overflow in any part of the front-end or build a very large and fast signaling network which can throttle the level 0 trigger when any front-end buffer risk to overflow.
To obtain such a tight synchronization between so many channels the architecture of each sub-system must conform strictly to a common architecture definition. To insure that the real system actually obtains and maintains the required synchronization it will be necessary to include special synchronization checks on all data being collected in the system. In addition regular resets of the whole synchronization system must be performed to be sure to recover parts of the front-electronics system which may have lost synchronization because of a noise spike on a clock signal or a Single Event Upset (SEU) in the control logic of the front-end electronics caused by radiation effects.
The general physical placement of the front-end electronics in LHCb is split in two partitions. The analog front-end together with L0 pipeline and the L0 derandomizer buffer is located either directly inside the detector or on the outside of the detector. The Level 1 buffer and all its related electronics will be located in crates in the counting room. The front-end electronics located inside the detector must be capable of working correctly with radiation levels of up to several hundred krad/year (depending on detector). Electronics located in the cavern must be capable of working with radiation levels up to a few krad per year. The rate of single event upsets must be estimated for each sub system and the effect on its function and the related recovery time must be evaluated. Repair of electronics inside the detector can only be performed on a yearly basis. Electronics located inside the cavern can most likely only be accessed on a monthly basis.
Electronics in LHCb
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