Overview of front-end electronics
in LHCb sub-detectors.

The table below gives the currently best known overview of all the front-end electronics in the LHCb light configuration. Many parameters have been estimated by the electronics coordinator and any feedback to improve the correctness of the presented overview is highly appreciated

Printing hint: use landscape printing format, otherwise a large part of the table will be truncated.

Summary and assumptions can be found at the end of the page

Detector

Sub-detector Vertex Pileup RICH1&2 IT + TT Outer tracker SPD Preshower Ecal Hcal Muon
Number of channels: 172k 8k 200k +
295k
129k 
180k
54k 6k 6k 6k 1.5k 125k physical
26k logic
Detector type Silicon strip Silicon strip HPD with 
silicon Pixel
Silicon strip Straw tube MAPMT
64 ch.
MAPMT
64 ch.
PMT PMT MWC, 
High voltage <1kV <1kV 20kv + 1kV <1kV 2 kV <1kV < 1kV <1kV <1kV 3.5kV 
Measurement type: Amplitude/ binary Amplitude/
Binary
Binary Amplitude/ binary Drift time Binary Amplitude Amplitude Amplitude Binary
(TDC)
Average channel occupancy
(over time)
0.2% 0.2% 1%
0.3%
0.4% 2% 1% 1.3 %
> 0.75 Mips
1.1%
> 0.01 GeV
2.1 %
> 0.01 GeV
0.5%
(logical)
Maximum channel occupancy
(over time)
1.0% 1.0% 4%
1%
2% 5% 10% 10% 10% 6% 5%
(logical)
Detector efficiency 99% 99% 90% 99% 90%
per layer
99% 99% 99% 99% >90% (phy.)
>99% (logical)
Detector multiplicity 1.2 1.2 1.1 1.2 1 1 1.2 2 2 1.2
Detector sensitivity: 12500e/Mips 12500e/Mips 5000e/Mips 25000e/Mips 50fC/Mips ? 7500e/Mips 1000e/GeV 50e/GeV 40fC/Mips
Minimum signal: 1/2Mips 1/2Mips 1/2Mips 1/2Mips   1/2Mips 1/2 Mips 1/2Mips
Maximum signal 10Mips 10Mips 5Mips 10Mips 10Mips 10Mips 10 Mips 200GeV 300GeV 10Mips
Noise level: <1000e <1000e <250e <1000e 1800e <1000e <1000e 2 fC 
@250pF
Signal/noise: 14 - 6 10 >8 10 14 8 8 20
Threshold: 6000e 6000e 2000e 6000e 2-3 fC 2000e 2000e 5-10fC
Noise occupancy: <0.1% <0.1% <0.1% <0.1% <0.1% <1% <1% <1% <1% <0.1%
Detector signal pulse width: <25ns <25ns <25ns <25ns <50ns <50ns <50ns <50ns <50ns <25ns
Pulse width after shaping: <25ns <25ns <75ns <25ns <25ns <25ns <25ns <25ns <25ns <50ns
Dead time 0 0 50ns 0 25-50ns 0 0 0 0 <25ns
Average data occupancy
(over accepted events)
0.7% 0.7% 0.4%
0.2%
0.4%
0.2%
5%
(two bunch periods)
7% 7%
> 0.75 Mips
7%
> 0.01 GeV
13%
> 0.01 GeV
1.5% (logical)
Maximum data occupancy
(over accepted events)
1.5% 1.5% 1.5%
1.5%
1.5% 10%
(two bunch periods)
20% 20% 18% 57% 5.0% (logical)
Dynamic range 
(in bits):
6-8 6-8 1 6-8 50ns (2x25ns) 1 10 12 12 1 (25ns)
Resolution 
(in bits):
4-6 4-6 1 4-6 1ns 1 8 10 10 1 (3ns)

Analog front-end

Sub-detector Vertex Pileup RICH1&2 IT + TT Outer tracker SPD Preshower Ecal Hcal Muon
Location of analog front-end: Included in 
L0 ASIC
Included in 
L0 ASIC
Included in L0 ASIC Included in L0 ASIC Top and bottom  of detector Top and bottom  of detector Top and bottom  of detector On L0-L1 board On L0-L1 board In detector
Radiation level for analog front-end over 10 years   <6.6krad <5.8krad <5.8Krad <4.8krad <4.8krad <500krad
Channels per analog front-end chip:   8 16 8 4 4 8
Number of analog front-end chips:   6750 375 750 1.5K 375 16K (Carioca)
8k (Dialog)
Analog front-end chip   ASDBLR CAL-SPD CAL-PRE CAL-ANA CAL-ANA Carrioca 
(analog)  

DIALOG 
(digital)

Power consumption of analog front-end chip   500mW 500mW 500mW 500mW 500mW 500mW
Channels per analog front-end board   32 64 64 32 32 16 Physical
Power consumption of analog front-end board   2.5W 2.5W 5W 1W
Number of analog front-end boards   1688 94 94 7632 +
152 (IB)
Power consumption of total analog front-end   4.2kW
Cooled

1kW 
Linear regulators
Cooled

Cable loss 1.25kw

0.25kW

Linear regulators 60w

Cable loss 80w

0.5 kW

Linear regulators 125w

Cable loss 150w

7.6kW +

Linear regulators 2kW

Cable loss 2.5kw

2.3kW (IB)
(cooled crate)

ECS access to analog front-end   I2C or eq. I2C or eq. I2C or eq.
ECS parameters per analog front-end chip
(bytes)
  16 4 4 4 8 + 2
Total ECS parameters for analog front-end (bytes)   6K 3K 6K 1.5K 200k +
1M (IB)

L0 front-end

Sub-detector Vertex Pileup RICH1&2 IT + TT Outer tracker SPD Preshower Ecal Hcal Muon
Link to L0 electronics     LVDS Diff. analog LVDS
Link distance     <10m <10m <10m
Number of links     6K 6K 42k to IB
26k logical
Data for L0 trigger: 8k/4/2=1k binary LVDS @80MHz

4x2x12fiber
8 x 12way ribbons

Binary

On 16 optical links to selection crate in counting

  8 bit Pt

On 112 optical links to selection crate in counting

8 bit Pt

On 80 optical links to selection crate in counting

Binary

1248 used fibers in 
120 ribbons

Local L0 trigger processing impact parameter, 
in counting
Extraction of maximum Pt candidates.
Particle type.
In cavern + counting
Max Pt candidates.
in counting
L0 pipeline type (analog/digital): Analog Analog Digital
Zero-sup. data.
Max 16 hits
Analog Digital Digital Digital Digital Digital
(TDC)
Location of L0 pipeline: In vacuum tank In vacuum tank In HPD vacuum tube In detector Top and bottom of detector On L0 board on top of ECAL On L0 board on top of ECAL On L0 board on side of detector
Radiation level over 10 years <5.8Mrad <5.8Mrad <24Krad
<8.5Krad
<7Mrad <6.6krad <4.8krad <4.8krad <7.9krad
L0 derandomizer size: >=16 >=16 >=16 >=16 >= 16 >=16 >=16 >=16
Multiplexing of derandomized data 32:1 32:1 32:1 32:1 32:1 32:1 32:1 32:1
L0 derandomizer read-out speed: <=900ns <=900ns <=900ns <=900ns <= 900ns) <=900ns <=900ns <=900ns
Channels per L0 front-end chip: 128 128 32 x 32= 1024 128 32 8
Number of L0 chips: 1344 64 196
288
1008 + 
1410
1688 3552
L0 front-end chip: Beetle Beetle Pixel Beetle OTIS Antifuse FPGA Antifuse FPGA SYNC
Power consumption of L0 chip: 1W 1 W 2W 1W 500mW 500mW
L0 chips per L0 board 16 16 2 Pixel
2 PINT
2 Ana pilot
1 TTCrx
1QPLL

2 GOL
3 4 OTIS
1 GOL
24
Channels per L0 board 2048 2048 2048 384 128 64 SPD + 64 preshower 32 192
Power consumption of L0 board 16W + 
16W repeater
16 W 6W 3W 3W 50w 50w 50w
Number of L0 boards 84 + 
84 repeaters
4 98 + 
144
336 + 
470
426 94 ECAL: 188
HCAL: 47
148
L0 crates           8 ECAL: 14
HCAL: 4
10
Total power consumption of L0 boards FE:
1.4kw cooled

Repeater:
1.4 kw

Linear regulators 0.7kw

Cable loss 1kw

FE: 
64W 
cooled

L0 trg links
200w
cooled

Linear regulators 40w

Cable loss 50w

FE:
0.6kw +
0.8kw

Linear regulators 0.5kW

Cable loss 0.5kw

FE:
1.0kw +
1.4kw
Cooled

Service box:
6x500w=3kw
4x500w=2kw
cooled

Cable loss 1.8kw

FE: 1.3kw
Cooled

0.3kw
Linear regulators 
Cooled

Cable loss 0.4kw

FE: 4.7 kw cooled crate FE: 12 kw cooled crate FE: 7.5kw
cooled crate
ECS access to L0 electronics I2C/JTAG via
SPECS
I2C via SPECS JTAG + I2C via SPECS I2C via SPECS JTAG, I2C via SPECS SPECS SPECS CAN
ECS parameters for L0 electronics (bytes) Per L0 chip:
gain: 1
shaping: 2
latency:1
calibration: 2
mode: 2
Total: 8
Per L0 chip:
gain: 1
shaping: 2
latency:1
calibration: 2
mode: 2
Thres:128
Total: 136
Per L0 chip
DACs: 42
thres: 3K
div: 2 K
Total: 5K
Per L0 chip:
gain: 1
shaping: 2
latency:1
calibration: 2
mode: 2
Total: 8
Per L0 chip:
Total: 10
Per channel: 4
Total: 512 bytes
Per channel: 4
Total: 128
Total ECS parameters for L0 front-end (bytes) 1344 x 8 =
11k
9k 196x5k=980k
262x5k=1310k
8k 
11k
1688x 10 =
17k
94 x 512 = 50k 235x128= 30k

L1 front-end

Sub-detector Vertex Pileup RICH1&2 IT + TT Outer tracker SPD Preshower Ecal Hcal Muon
Link type to L1 electronics: Analog differential 
twisted pair in 4pair cat6 cables
Analog differential 
twisted pair in 4pair cat6 cables
Digital optical
1.6 Gbits/s 
12 way ribbon
Service box with ADC and optical link driver 1.6Gbits/s.
One per Beetle.
12 way ribbon.
Digital
optical
1.6Gbits/s
12 way ribbon
Digital optical 1.6Gbits/s

2 x 12 ribbon per FE crate. Each link carries the equvivalent of one FE card

Digital
optical
1.6Gbits/s
12 way ribbon
Link distance: ~60m <60m <100m <100m <100m <100m <100m
Number of links 5376
(1344 x 4)
256
(64 x 4)
196 (17x12) +
288 (24x12)
1008 (84x12) + 
1410 (120x12)
426 (36x12) 16 -> 14 12way ribbons
via patch panels
24 -> 20 12way ribbons via patch panel 8 -> 6 12way ribbons via patch panel 148
Input links to L1 module: 64 64 2 x 12 ribbon 2 x 12 ribbon 2 x 12 ribbon 2 x 12ribbon 2 x 12 ribbon
Channels per L1 module: 2048 2048 24576 3072 3072 max 1024 SPD
max 1024 Pre.
max 768 4608 logical channels
Number of L1 modules: 84 4 9
11
42 + 
60
18 8 10 4 10
L1 modules for L0 trigger   1       1 (8)
L1 module ref: TELL TELL RICH-L1 TELL TELL TELL TELL
Maximum total power consumption of L1 boards 8.4kW
cooled crate
0.5kW
cooled crate
0.9kW +
1.2kW
cooled crate
4.2kW
6.0kW
cooled crate
1.8kW
cooled crate
2.3kW
cooled crate
1.8kw
cooled crate
ECS access to L1 electronics CC-PC CC-PC CC-PC or SPECS CC-PC CC-PC CC-PC CC-PC
ECS parameters per L1 module (bytes) FPGA: 1M FPGA: 1M FPGA: 1M FPGA: 1M FPGA: 1M FPGA: 1M FPGA: 1M FPGA: 1M
Total ECS parameters for L1 modules (bytes) 84M 4M 9M
12M
42M
60M
18M 8M 10M 4M 8M
Zero-suppression: Ped-comp. Ped-comp. Address Ped-comp. Time extract
Performed in TDC
None Thres-sur. Thres-sur. Address
Zero-suppressed data format 2 bytes:
8 bit address
8 bit data
2 bytes:
8 bit address
8 bit data
2 bytes:
16 bit address
2 bytes:
8 bit address
8 bit data
2 bytes:
8 bit address
8 bit time
Binary
4 bytes:
 16 bit addr.
 10 bit data
4 bytes:
12 bit address +
12 bit data + 8bit trig.
2 bytes:
8 bit addr.
8 bit TDC
DAQ links 84 4 + 1 9
12
42 + 
60
18 8 10 4 10 + (8)
Average event size per L1 module (bytes) 44+40 44+40 295+40
148+40
37+40
18+40
460+40 192 + 430 + 40 322+40 600+40 207 +40
Data rate per L1 module  
@1Mhz L0
bytes/s
85M 85M 335M
188M
78M
58
M
550M 675M 375M 650M 250M
Number of L1 crates 5 1 1
1

4
1 2 1

TFC

Sub-detector Vertex Pileup RICH1&2 IT + TT Outer tracker SPD Preshower Ecal Hcal Muon
Number of TTCrx
Not including spares
L0: 84
L1: 84
12 98 + 9
144 + 12
12 + 42
8 + 60
L0: 24
L1: 18
FE crates: 26
Trigger: 20
TELL1: 22
FE: 148
L1: 10
Trg.: 4
Splitters (1:32) L0: 4
L1: 4
1 5
6
1 + 2
1
+ 2
L0: 1
L1: 1
3 FE: 8
L1: 1
Trg: 1
TTCtx (14 outputs) 1 1 2 (RICH 1+2) 2 (IT + TT) 1 3 (SPD/PRE + Ecal + Hcal) 1

Crates, racks and power

Sub-detector Vertex Pileup RICH1&2 IT + TT Outer tracker SPD Preshower Ecal Hcal Muon
Crates in cavern 1 (SPECS) 1 (SPECS)
1 (optical)
1 (SPECS)
1 (SPECS)
  1 (SPECS) 8 FE 14 FE 4 FE 10 L0
12 IB
Racks in cavern 1 (SPECS) 1 1 (SPECS)
1 (SPECS)
  1 (SPECS) 2 FE 4 FE 2 FE 10
Power dissipation in cavern L0 FE:
1.4 kW
cooled

Repeater:
1.4kW

Linear regulators 0.7kw

Cable loss 1kw

ECS: 
100W
cooled crate

L0 FE: 
64w 
cooled

L0 trg link:
200W
cooled crate

Linear regulators 40w

Cable loss 50w

ECS:
100W
cooled crate

L0 FE:
0.6 KW +
0.8 KW

Linear regulators 0.5kw

Cable loss 0.5kw

ECS: 
200W
cooled crate

L0 FE:
1.0kW +
1.4kW
Cooled

Service box:
3kW +
2kW
Cooled

Cable loss 1.8kw

Analog: 
4.2 kw
Cooled

L0 FE: 
1.3 kW
Cooled

Linear regulators 1.5kw
Cooled

Cable loss 1.25kw + 0.4kw

Analog FE:
0.25 kw
0.5 kw

Linear regulators 0.2kw

Cable loss 0.23kw

ana. PS: 0.2 kw
L0
FE: 4.7 kw
Trg: 1.6 kw
PS: 2 kw
cooled crate

FE: 12 kw
Trg: 3kw
PS: 4 kw
cooled crate

 

 

Analog:
7.6 kW

Linear regulators 2kw

Cable loss 2.5kw

ana. PS: 3 kW
IB: 2.3 kW
PS: 0.5 kW
cooled crate

L0 FE:
8 kW
PS: 2 kW
cooled crate

Crates in counting 5 L1 1 L1
1 Trig.
2 L1 7 L1 1 L1 2 L1
1 L0 trig
1 L1
4 L0 trig
Racks in counting 2 L1 FE
1 HV & LV
1 spare
1 L1 + Trg.
1 spare
2 RICH1
2 RICH2
1 spare
2 L1 FE
2 HV, LV
1 spare
1 L1 FE
2 HV, LV
1 spare
1 L1
1 L0 trig
2 HV, LV
1 spare
1 L1
2 L0 trig
2 HV + LV
1 spare
Power dissipation in counting HV: 1 kW
cooled crate

FE PS: 1.1kW
cooled crate

L1: 9.6 kW
PS: 2.4kW
cooled crate

HV: 40W
cooled crate

FE PS: 40W
cooled crate

L1: 0.5kW
Trg: 0.8kW
PS: 0.3kW
cooled crate

HV: 1kW
cooled crate

FE PS: 0.5kW
cooled crate

L1: 2.1 kW
PS: 0.5 kW
cooled crate

HV: 1kW
cooled crate

FE PS: 2.3kW
cooled crate

L1: 10.2 kW
PS: 2.5kW
cooled crate

HV: 1kW
cooled crate

FE PS: 1.4kW
cooled crate

L1: 1.8 KW
PS: 0.4 kW
cooled crates

HV: 1kW
cooled crate

L1:2.2 kW
PS: 0.5 kW
cooled crate

Trig: 2 kW
PS: 0.5 kW
cooled crate

HV: 1kW
cooled crate

L11kW
PS: 0.2 kW
cooled crate

Trig: 
7.6 kW
PS: 1.9kW
cooled crated

Power supplies

Sub-detector Vertex Pileup RICH1&2 IT + TT Outer tracker SPD Preshower Ecal Hcal Muon
HV 84 units
max 1000 V
? mA
Counting
4 units
max 1000 V
? mA
Counting
28 + 36 units
20 kV
? mA
Counting

28 + 36 units
max 1000 V
? mA
Counting

20 units
max 1000 V
? mA
Counting
844 units
2 kV
? mA
Counting
188 units
1 k V
? mA
Counting
188 units
1 k V
? mA
Counting
188 units
1 k V
? mA
Counting
47 units
1 k V
? mA
Counting
84 units
3.5 k V
? mA
Counting
Analog front-end         ? units
2.5 V
? A
Counting
? units
? V
? A
Counting
? units
? V
? A
Counting
    Analog FE:
? units
2.5 V
? A
Cavern

Digital FE:
? units
2.5 V
? A
Cavern

10 IB crates:
2.5 V
? A
Cavern

L0 front-end FE:
84 units
2.5 V 
8 A
Counting

Repeaters:
84 units
+/- 5v
6 A
Counting

FE:
4 units
2.5 V 
8 A
Counting

Service box:
? units
2.5 V
? A
Counting

Trig link:
? units
2.5V
? A
Counting

Pixel:
28+36 units
1.2 V
? A
Counting

PINT+ PILOT+ QPLL+ GOL:
28+36 units
2.5V
? A
Counting

TTCrx:
28+36 units
3.3V
? A
Counting

FE:
20 units
2.5 V
? A
Counting

Service box:
10 units
2.5 V
? A
Counting

FE:
? units
2.5v
? A
Counting
8 FE crates: 
Cavern

5 V
? A

3.3 V
? A

? V
? A

 
14 FE crates:
Cavern

5 V
? A

3.3 V
? A

? V
? A

 
4 FE crates:
Cavern

5 V
? A

3.3 V
? A

? V
? A

 
10 FE crates:
Cavern

5 V
? A

3.3 V
? A

? V
? A

 
L0 trigger  

1 crate
Counting

5 V
? A

3.3 V
? A

? V
? A

     

1 crate
Counting

5 V
? A

3.3 V
? A

? V
? A

5 crates
Counting

5 V
? A

3.3 V
? A

? V
? A

DIV                  

Cables through radiation wall,   Detailed detector cabling on other web page

 

Summary

Channels

1 Million

Single ended analog links

6k (Ecal) + 1.5k (Hcal) = 7.5k

Differential analog links 6k (Preshower)

Differential LVDS links

1k (pileup) + 6k (SPD) + 60k(muon) 

ASIC's

3826 Beetle-SCT (Velo + IT + TT + Pileup)
484   Pixel (RICH)
484   Pint (RICH)
484   Analog pilot
6750  ASD (OT)
1688 OTIS (OT)
375   CAL-SPD (SPD)
750   CAL-PRE (Preshower)
2000 CAL-ANA (Ecal + Hcal)
16000  Carioca (Muon)
8000 DIALOG (muon)
3552  SYNC (muon)
5000 GOL
1000 TTCrx
Total: ~ 50k

Multiplexed differential analog links

5376 (Vertex)

L0 crates 36

L1 modules

271

L1 crates

19

Optical 1.6 Gbit/s links

8 x 12ribbon Pileup (trg)
204 x 12 ribbon IT+TT
24 x12 ribbon RICH
36 x 12 ribbon OT
208 (trg) CAL.
120 x 12 ribbon (trg) + 148 MUON

Total: ~5500

Average event size

~40 kBytes

ECS data ~4 Mbytes for analog + L0 front-end
~1 Gbytes for L1 electronics (FPGA configuration)
Crates in cavern Sub-detectors:            53
Velo:                        1 (ECS)
Pileup:                     2 (ECS + trigger links)
RICH:                      2 (ECS)
IT:                            0
OT:                          1 (ECS)
Cal:                          26 (L0 front-end)
Muon:                    22
(L0 front-end)
Racks in cavern Sub-detectors:            23
Velo:                        1 (ECS)
Pileup:                     1
RICH:                      2 (ECS)
IT:                            0
OT:                          1 (ECS)
Cal:                          8
Muon:                    10

Others:                        ?

Power dissipation in cavern

Not cooled:               20 kw (muon dominated)
Velo:                         3.1 kw
Pileup:                      0.1
RICH:                       0.5 kW
IT:                             1.8 kw
OT:                           1.65 kw
Cal:                           1.2 kw
Muon:                     12.1 kw

Cooled:                      18 kw
Velo:                            1.4 kw
Pileup:                         0.06 kw
RICH:                          1.9 kw
IT:                               7.4 kw
OT:                             7.0 kw
Cal:                              0
Muon:                        0

Cooled crates:           63 kw (cal dominated)
Velo:                           0.1 kw
Pileup:                        0.3 kw
RICH:                         0.2 kw
IT:                               0
OT:                             0
Cal:                             46 kw
Muon:                       15.8 kw

Magnet:                          ?

Others:                           ?

Crates in counting Sub-detectors:            30
Velo:                        5
Pileup:                     2
RICH:                      2
IT:                            7
OT:                          1
Cal:                          3
Muon:                    5
L0-du:                     1
TFC:                       4
Racks in counting Sub-detectors:              37 ( D3)
Velo:                        4
Pileup:                     2
RICH:                      5
IT:                            5
OT:                          4
Cal:                          5
Muon:                    6

L0-du:                    1
TFC:                       2
LHC interface:      1
DSS:                       1

DAQ:                       58 (D1+D2)
Switch:                      8
Farm:                          50

ECS:                        6 (D2)

Gas systems:            ?

Magnet:                   ?

Others:                     ?

Power dissipation in counting
(cooled crates)
Total:                               ~535 kw

Sub-detectors:             60 kw
Velo:                        14.1 kw
Pileup:                     1.7kw
RICH:                      4.1 kw
IT:                            16 kw
OT:                          4.6 kw
Cal:                          6.2 kw
Muon:                    11.7 kw
L0-DU:                    1 kw

DAQ:                        1800x250w = 450kw

ECS:                         100x250w = 25kw

Magnet power supply: ?

Others:                        ?
Gas systems        ?
Mains distribution: ?

Power consumption Total:                   640 kw
Velo:                            19 kw
Pileup:                         2.1 kw
RICH:                          6.7 kw
IT:                               25.2 kw
OT:                             13.3 kw
Cal:                             53.4 kw
Muon:                       39.6 kw
L0-DU:                       1 kw
TFC:                           1  kw    
LHC interface:          1 kw
ECS:                           25 kw
DAQ:                         450 kw
DSS:                           2kw

Gas systems
Cooling systems
Other

 

Sub-detector assumptions

Vertex: The analog front-end and the L0 pipeline with its L0 derandomizer is contained in the Beetle ASIC located inside the vacuum vessel of the detector. Multiplexed analog data from the L0 derandomizer is transported out of the vacuum vessel on a large set of differential twisted pairs, via repeater boards, to the TELL1 with 64 digitizing inputs.

Pileup-veto:  The Beetle front-end chip, containing the analog front-end and the L0 pipeline, is located inside the vacuum vessel of the Vertex detector. Binary data for the L0 trigger from four front-end channels are Ored together and multiplexed at 80 MHz and transported out of the vacuum vessel as LVDS signals. In the vicinity of the vacuum vessel the L0 binary trigger data is converter into optical links on fiber ribbons and transported to the L0 trigger processing unit in the counting room. The readout of analog channel data to the DAQ system is performed with a system equivalent to the Velo. Binary data used in the trigger processing is read out with an additional TELL1 module.

RICH: A pixel HPD detector, located in a vacuum tube, extracts binary channel data and stores it during the L0 latency. Accepted data is readout out on 32 signals each covering 32 pixels. One 1.6Gbits/s optical link is used to transport data from one HPD tube to the L1 electronics with 24 inputs located in the counting room.

Inner tracker: 3 Beetle front-end chips, containing the analog front-end and the L0 pipeline, are located on hybrids inside the detector. Multiplexed analog data is transported out of the detector to a service box located on the same support frame but out of the detector acceptance. The analog data is digitized in the service box and transported to the TELL1 in the counting room on optical fibers in 12 way fiber ribbons.

Outer tracker: The analog front-end for the straw tubes are located directly at the end of the straws (top and bottom of the detector). The discriminated detector signals are connected to a board with four 32 channel TDCs (Time to Digital Converter). Data from the four TDC's are multiplexed and sent on a 1.6Gbits/s optical link to TELL1 modules with 24 optical inputs.

SPD and Preshower: The SPD signal from a 64 channel MAPMT is amplified, shaped and discriminated by custom front-end chips, mounted on the top and bottom of the detector, and driven to nearby crates on twisted pairs. The analog Preshower signal from a 64 channel MAPMT is amplified and shaped by custom front-end chips, mounted on the top and bottom of the detector, and driven to nearby crates on differential analog links. All further front-end processing is performed on a combined SPD - Preshower front-end card located in crates on top of the calorimeter detectors. The first stage of L0 trigger processing is performed directly in the front-end crates. Final L0 trigger processing is performed in the calorimeter trigger crates in the counting room. The interface to the DAQ system is  handle by TELL1 modules.

ECAL and HCAL: These two detectors are assumed to be so similar that identical front-end electronics are used. The PMT signal is transported out of the detector on high quality coaxial cables to crates on top of the calorimeter detectors where all further front-end signal processing is performed. Final L0 trigger processing is performed in the calorimeter trigger crates in the counting room. The interface to the DAQ system is handled by TELL1 modules.

Muon: The detector signal is amplified and discriminated inside the detector. It is assumed that the mapping from physical channels to logical channels is performed on the analog front-end card itself and on Intermediate boards (IB) located at the edge of the detector. The logical channels are driven on twisted pairs to nearby crates with the remaining front-end electronics. Synchronized binary data is sent on optical links from the front-end modules in the cavern to the muon trigger system located in the counting room. Data from the front-end electronics modules are sent on optical links to TELL1 modules in the counting room.

 

General assumptions

9U boards : 9U sized boards is in general assumed used for most front-end electronics boards not located directly inside detectors. The large board size enables a large number of channels to be integrated on each module. The power consumption of a typical 9U module is estimated to be maximum 100watt.

ECS: Experiment Control System. The higher levels of this communication network will be based on local-area networks but at the lowest levels of the front-end electronics more specialized interfaces will be use ( Ethernet, SPECS, CAN, I2C, JTAG, etc.).

Power supplies: An additional power dissipation related to the power supplies for both the cavern and the counting room is added. It is assumed that switching mode power supplies have an overall efficiency of 75% (25 % loss).

Definitions

Average channel occupancy: Defined as the average percentage of bunch crossings (not real interactions) where a particle hit is detected on a detector channel. This occupancy must be averaged over all types of interactions and take into account background rates, the number of interactions per bunch crossing (includes both triggered an not triggered events) and the LHC bunch structure. This occupancy can be used to estimate effects of channel dead time and the number of channel hits that have to be buffered during the L0 latency (mainly important for RICH having a zero-suppressed L0 latency buffer) .
This can NOT be used to estimate event sizes to DAQ as it does not include multiplicity, crosstalk, noise and the fact that events are selected by two trigger levels. See average data occupancy

Maximum channel occupancy: Similar to the previous but taken over a small local area of the detector where the particle rate per detector channel is the highest.

Detector efficiency: Percentage of particles traversing a plane of detector elements generating a real detector signal.

Detector multiplicity: Average number of detector channels in a detector plane giving a signal for one detected particle (including crosstalk).

Noise occupancy: Percentage of channels generating a noise hits.

Average data occupancy: This is the occupancy which determines the amount of data to be sent to the DAQ system. It is defined as the percentage of channels per triggered event (passing both L0 and L1 trigger) which has non-zero data. The effects of channel occupancy, noise, crosstalk and the event selection in the trigger systems must be taken into account.

Maximum data occupancy: Similar to previous but taken over a group of channels with the highest occupancy, belonging to the same logical unit (L1 electronics module).

Zero suppression: To reduce the amount of data to send to the DAQ system all data accepted by the L0 trigger must be zero suppressed by one of the following schemes:

Zero-suppression processing time: The absolute maximum processing time available to perform zero-suppression is 9us given by the maximum 100KHz L1 trigger rate.

Zero-suppressed data format: It is assumed that a local 8 (16) bit channel address is sufficient when using a hierarchical channel identification scheme. Additional channel identification addressing is included in a 50% data overhead (see: Average event size per L1 module).

Average event size per L1 module: The average event size per L1 module is estimated as follows:
(Average data occupancy x Channels per L1 board x Number of bytes per channel having data) x 1.5 + 40 bytes event building framing.
Includes a 50% data formatting overhead.

Data rate per L1 module: Calculated as the product of the Average event size per L1 module and the nominal L0 trigger rate (1MHz).

Average event size: Calculated at the output of the L1 front-end electronics. A 50% data overhead is included in the event size (see: Average event size per L1 module).

This page was last modified by JC on May 16, 2006. This page has been accessed Hit Counter number of times.