Notes from Strip-chip discussion with Marek, 24th February 2012

Marek described their good progress in Krakow. They have just submitted a design for a 10-bit SAR ADC in IBM 130nm and are waiting for the chip. This was their first submission in this process so was a good 'learning experience'.

They have looked at an ADC design for LHCb, and a 6-bit ADC is a little easier to implement than 5 bits. They are confident that the layout will fit into the specified 40um pitch. The goal is to submit this in the May MPW to IBM.
This ADC requires a PLL to make the SAR clock. A prototype PLL will be tested as part of the 10-bit ADC. We agreed that the final solution should be a PLL based on the 40MHz clock reference (provided by the GBT).

Marek agreed to provide a power estimate of this ADC design.

Front-end shaper: Marek expressed doubts about meeting the specification of 5% pulse remainder after 25ns. This will be difficult (impossible) with unipolar shaping and a peaking time of 25ns. Two possible solutions are:
1. Allow an undershoot (bipolar shaping) but we then have to be careful with the recovery time
2. Shape faster to reduce the peaking time, and hence the recovery time.
He agreed to look into these options.
We agreed that they should try to submit a front-end with ADC (8 channels) in the November MPW to IBM.

Marek has funding available for submissions for this year. Beyond that, other sources of money have to be found. The manpower (students) in Krakow should also be maintained.