Overview of front-end electronics
in LHCb sub-detectors.

The table below gives the currently best known overview of all the front-end electronics in the LHCb light configuration. Many parameters have been estimated by the electronics coordinator and any feedback to improve the correctness of the presented overview is highly appreciated

Printing hint: use landscape printing format, otherwise a large part of the table will be truncated.

Summary and assumptions can be found at the end of the page

Summary

Sub-detector assumptions

Vertex: The analog front-end and the L0 pipeline with its L0 derandomizer is contained in the Beetle ASIC located inside the vacuum vessel of the detector. Multiplexed analog data from the L0 derandomizer is transported out of the vacuum vessel on a large set of differential twisted pairs, via repeater boards, to the TELL1 with 64 digitizing inputs.

Pileup-veto:  The Beetle front-end chip, containing the analog front-end and the L0 pipeline, is located inside the vacuum vessel of the Vertex detector. Binary data for the L0 trigger from four front-end channels are Ored together and multiplexed at 80 MHz and transported out of the vacuum vessel as LVDS signals. In the vicinity of the vacuum vessel the L0 binary trigger data is converter into optical links on fiber ribbons and transported to the L0 trigger processing unit in the counting room. The readout of analog channel data to the DAQ system is performed with a system equivalent to the Velo. Binary data used in the trigger processing is read out with an additional TELL1 module.

RICH: A pixel HPD detector, located in a vacuum tube, extracts binary channel data and stores it during the L0 latency. Accepted data is readout out on 32 signals each covering 32 pixels. One 1.6Gbits/s optical link is used to transport data from one HPD tube to the L1 electronics with 24 inputs located in the counting room.

Inner tracker: 3 Beetle front-end chips, containing the analog front-end and the L0 pipeline, are located on hybrids inside the detector. Multiplexed analog data is transported out of the detector to a service box located on the same support frame but out of the detector acceptance. The analog data is digitized in the service box and transported to the TELL1 in the counting room on optical fibers in 12 way fiber ribbons.

Outer tracker: The analog front-end for the straw tubes are located directly at the end of the straws (top and bottom of the detector). The discriminated detector signals are connected to a board with four 32 channel TDCs (Time to Digital Converter). Data from the four TDC's are multiplexed and sent on a 1.6Gbits/s optical link to TELL1 modules with 24 optical inputs.

SPD and Preshower: The SPD signal from a 64 channel MAPMT is amplified, shaped and discriminated by custom front-end chips, mounted on the top and bottom of the detector, and driven to nearby crates on twisted pairs. The analog Preshower signal from a 64 channel MAPMT is amplified and shaped by custom front-end chips, mounted on the top and bottom of the detector, and driven to nearby crates on differential analog links. All further front-end processing is performed on a combined SPD - Preshower front-end card located in crates on top of the calorimeter detectors. The first stage of L0 trigger processing is performed directly in the front-end crates. Final L0 trigger processing is performed in the calorimeter trigger crates in the counting room. The interface to the DAQ system is  handle by TELL1 modules.

ECAL and HCAL: These two detectors are assumed to be so similar that identical front-end electronics are used. The PMT signal is transported out of the detector on high quality coaxial cables to crates on top of the calorimeter detectors where all further front-end signal processing is performed. Final L0 trigger processing is performed in the calorimeter trigger crates in the counting room. The interface to the DAQ system is handled by TELL1 modules.

Muon: The detector signal is amplified and discriminated inside the detector. It is assumed that the mapping from physical channels to logical channels is performed on the analog front-end card itself and on Intermediate boards (IB) located at the edge of the detector. The logical channels are driven on twisted pairs to nearby crates with the remaining front-end electronics. Synchronized binary data is sent on optical links from the front-end modules in the cavern to the muon trigger system located in the counting room. Data from the front-end electronics modules are sent on optical links to TELL1 modules in the counting room.

General assumptions

9U boards : 9U sized boards is in general assumed used for most front-end electronics boards not located directly inside detectors. The large board size enables a large number of channels to be integrated on each module. The power consumption of a typical 9U module is estimated to be maximum 100watt.

ECS: Experiment Control System. The higher levels of this communication network will be based on local-area networks but at the lowest levels of the front-end electronics more specialized interfaces will be use ( Ethernet, SPECS, CAN, I²C, JTAG, etc.).

Power supplies: An additional power dissipation related to the power supplies for both the cavern and the counting room is added. It is assumed that switching mode power supplies have an overall efficiency of 75% (25 % loss).

Definitions

Average channel occupancy: Defined as the average percentage of bunch crossings (not real interactions) where a particle hit is detected on a detector channel. This occupancy must be averaged over all types of interactions and take into account background rates, the number of interactions per bunch crossing (includes both triggered an not triggered events) and the LHC bunch structure. This occupancy can be used to estimate effects of channel dead time and the number of channel hits that have to be buffered during the L0 latency (mainly important for RICH having a zero-suppressed L0 latency buffer) .
This can NOT be used to estimate event sizes to DAQ as it does not include multiplicity, crosstalk, noise and the fact that events are selected by two trigger levels. See average data occupancy

Maximum channel occupancy: Similar to the previous but taken over a small local area of the detector where the particle rate per detector channel is the highest.

Detector efficiency: Percentage of particles traversing a plane of detector elements generating a real detector signal.

Detector multiplicity: Average number of detector channels in a detector plane giving a signal for one detected particle (including crosstalk).

Noise occupancy: Percentage of channels generating a noise hits.

Average data occupancy: This is the occupancy which determines the amount of data to be sent to the DAQ system. It is defined as the percentage of channels per triggered event (passing both L0 and L1 trigger) which has non-zero data. The effects of channel occupancy, noise, crosstalk and the event selection in the trigger systems must be taken into account.

Maximum data occupancy: Similar to previous but taken over a group of channels with the highest occupancy, belonging to the same logical unit (L1 electronics module).

Zero suppression: To reduce the amount of data to send to the DAQ system all data accepted by the L0 trigger must be zero suppressed by one of the following schemes:

• Ped/com-comp.: Pedestal and common mode compensated thresholding continuously keeps track of the pedestal level on each channel and performs a thresholding after subtracting the current pedestal/common mode value.

• Thres-sur.: Thresholding with high thresholds and forcing all neighbor cells to be included in data set.

• Time-extract: Extraction of leading edge time.

• Address: Extracting channel addresses of channels being hit (for binary detectors).

Zero-suppression processing time: The absolute maximum processing time available to perform zero-suppression is 9us given by the maximum 100KHz L1 trigger rate.

Zero-suppressed data format: It is assumed that a local 8 (16) bit channel address is sufficient when using a hierarchical channel identification scheme. Additional channel identification addressing is included in a 50% data overhead (see: Average event size per L1 module).

Average event size per L1 module: The average event size per L1 module is estimated as follows:
(Average data occupancy x Channels per L1 board x Number of bytes per channel having data) x 1.5 + 40 bytes event building framing.
Includes a 50% data formatting overhead.

Data rate per L1 module: Calculated as the product of the Average event size per L1 module and the nominal L0 trigger rate (1MHz).

Average event size: Calculated at the output of the L1 front-end electronics. A 50% data overhead is included in the event size (see: Average event size per L1 module).

This page was last modified by JC on May 16, 2006. This page has been accessed number of times.